A memory cell of the one-time-programmable type generally comprises a capacitor, for example of the MOS type, possessing a dielectric layer between its two electrodes and operates as an anti-fuse whose state is modified in an irreversible manner, for example through breakdown of the dielectric layer, by applying a high programming voltage to the memory cell, in such a way that the memory cell passes from a non-conducting state to a conducting state, this amounting to changing its resistance.
In advanced CMOS technologies, elevated source and drain regions of the transistors, for example planar CMOS transistors, FinFET transistors or transistors produced on a substrate on insulator, for example a substrate of the FDSOI (“Fully Depleted Silicon-On-Insulator”) type, are formed by epitaxy.
A substrate of the silicon on insulator type comprises a semiconductor film, made for example of silicon or silicon alloy, such as a silicon-germanium alloy, situated above a buried insulating layer, commonly referred to by the acronym “BOX” (“Buried OXide”) itself situated above a carrier substrate, for example a semiconductor well.
In an FDSOI substrate, the silicon film is fully depleted (the semiconductor material is intrinsic) and has a particularly low thickness of the order of a few nanometers.
The use of elevated source and drain regions makes it possible to solve problems of reliability, such as the hot carrier reliability (HCI: Hot Carrier Injection) of the transistors and also the problem of the mechanical resilience of the metal silicide.
In general, the MOS capacitors of OTP memory cells are produced jointly with the MOS transistors by using similar method steps.
However, these epitaxied elevated regions do not have any impact on the performance of the MOS capacitors, both as regards the breakdown of the dielectric layer, and as regards the reading voltage, the leakage of the capacitor or else others of these electrical characteristics.